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Ordering number : ENN6976A
CMOS IC
LC72151V
PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems
Overview
The LC72151V is a PLL frequency synthesizer for car audio systems. It can implement high-performance multifunction tuners such as RDS tuners and features a fast locking circuit.
Functions
* High-speed programmable divider -- FMIN: 10 to 160 MHz: Pulse swallower type -- AMIN: 2 to 40 MHz: Pulse swallower type 0.5 to 10 MHz: Direct division type * IF counter -- HCTR: 0.4 to 25 MHz: for FM IF count -- LCTR: 10 to 500 kHz: for AM IF count 1.0 to 20 x 103 Hz: for frequency measurement * Reference frequency -- One of 11 frequencies may be selected (when a 10.25 or 10.35 MHz crystal is used) 50, 30*, 25, 12.5, 10, 9*, 6.25, 5, 3.125, 3*, 1 kHz Note: Cannot be used when a 10.25 MHz crystal is used * Phase comparator -- Supports dead band control -- Built-in unlock detection circuit -- Built-in deadlock clearing circuit * Built-in amplifier for forming an active low-pass filter -- Built-in operational amplifier for FM high-speed locking -- Built-in MOS transistor for AM tuning * Built-in crystal oscillator output buffer
* CCB is a trademark of SANYO ELECTRIC CO., LTD.
* I/O ports -- General-purpose I/O: 2 pins -- Four input ports (maximum) -- Three output ports (maximum) * Serial data I/O -- Supports communication with the controller in the CCB format. * Operating ranges -- Supply voltage: 4.5 to 5.5 V (VDD) 7.5 to 9.5 V (AVDD) -- Operating temperature: -40 to +85C * Package -- SSOP30
Package Dimensions
unit: mm 3191A-SSOP30
[LC72151V]
30 16
5.6
9.75
0.22
0.65
(0.43)
0.1
(1.3) 1.5max
1
15
0.15
SANYO: SSOP30
* CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
82102TN (OT) / 83101RM (OT) No. 6976-1/29
0.5
7.6
LC72151V Pin Assignment
LC72151V
XOUT
1
30 XIN 29 CE 28 DI 27 CL 26 DO 25 AOUT2
AVSS
I/O-1
2
S
I/O-2
3
S
XBUF
4
S
O-3
5
VDD
6
VSS
7
24 AIN2 23 PDM2 22 PDF
FMIN
8
AMIN
9
HCTR/I-3 10 LCTR/I-4 11 AREF 12 AVDD 13 AVSS 14 AOUT1 15
21 PDM1 20 PDS
19 AIN1 18 TGI1 17 TGI2
- +
16 TGO
(Top view)
No. 6976-2/29
LC72151V Block Diagram
XBUF
XIN XOUT
REFERENCE DIVIDER
PHASE DETECTOR CHARGE PUMP
PDM1 PDS PDM2 PDS
FMIN
SWALLOW COUNTER 1/16,1/17 4bits
UNLOCK DETECTOR
TGI1 TGI2 TGO
AMIN
12bits PROGRAMMABLE DIVIDER
CHARGE PUMP for FAST LOCK
PDF
AIN2 HCTR/I-3 UNIVERSAL COUNTER DATA SHIFT REGISTER LATCH FAST LOCK UP CONTROL AOUT2
AVDD LCTR/I-4 CCB I/F POWER ON RESET AIN1 AREF AVSS AOUT1
VDD VSS
CE
DI
CL
DO
I/O-1 I/O-2
O-3
No. 6976-3/29
LC72151V
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = AVSS = 0 V
Parameter Supply voltage Symbol VDD max VIN1 max Maximum input voltage VIN2 max VIN3 max VIN4 max VO1 max Maximum output voltage VO2 max VO3 max VO4 max IO1 max Maximum output current IO2 max IO3 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD * AVDD * CE, CL, DI XIN, FMIN, AMIN, HCTR/I-3, LCTR/I-4, AIN2, TGI1, TGI2, TGO I/O-1, I/O-2 AIN1, AREF DO XOUT, PDM1, PDM2, PDS, PDF, XBUF, TGI1, TGI2, TGO I/O-1, I/O-2, O-3, AOUT2 AOUT1 I/O-1, I/O-2, O-3 DO, TGI1, TGI2, TGO, AOUT1, AOUT2 XBUF (Ta 85C) Pin Ratings -0.3 to +6.5 -0.3 to +11.0 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +15.0 -0.3 to +6.5 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +15.0 -0.3 to +11.0 0 to 10.0 0 to 5.0 0 to 3.0 SSOP30 :160 -40 to +85 -55 to +125 mW C C mA Unit V
V
V
Note: Power must be applied to AVDD before applying to VDD and AVDD must be higher than or equal to VDD. Capacitors of at least 0.1 F must be inserted between the VDD and VSS, and between the AVDD and AVSS power supply pins.
Allowable Operating Ranges at Ta = -40 to 85C, VSS = AVSS = 0 V
Parameter Symbol VDD1 Supply voltage VDD2 VDD3 VIH1 High-level input voltage VIH2 VIH3 VIL1 VIL2 VO1 Output voltage VO2 VO3 fIN1 fIN2 fIN3 Input frequency fIN4 fIN5 fIN6 fIN7 VDD AVDD VDD CE, CL, DI I/O-1, I/O-2 HCTR/I-3, LCTR/I-4 CE, CL, DI, I/O-1, I/O-2, LCTR/I-4 HCTR/I-3 DO AOUT1 I/O-1, I/O-2, O-3, AOUT2 XIN FMIN AMIN (SNS=1) AMIN (SNS=0) HCTR/I-3 LCTR/I-4 LCTR/I-4 VIN1 *1 VIN2 *1 VIN3 *1 VIN4 *1 VIN5 *1 VIN6 *1 VIN7 *2 Pin VDD AVDD VDD AVDD Serial data retention voltage Conditions Ratings min 4.5 7.5 2.0 0.7VDD 0.7VDD 0.7VDD 0 0 0 0 0 7 10 2 0.5 0.4 10 1.0 6.5 13 VDD 0.3VDD 0.2VDD 6.5 9.5 13 11 160 40 10 25 500 20 x 103 kHz Hz MHz V V 8.5 typ max 5.5 9.5 V Unit
Low-level input voltage
V
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No. 6976-4/29
LC72151V
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Parameter Symbol VIN1 VIN2-1 VIN2-2 VIN2-3 VIN3 Input amplitude VIN4 VIN5-1 VIN5-2 VIN6-1 VIN6-2 VIN6-3 Guaranteed crystal oscillator frequency ranges X'tal XIN FMIN FMIN FMIN AMIN (SNS=1) AMIN (SNS=0) HCTR/I-3 HCTR/I-3 LCTR/I-4 LCTR/I-4 LCTR/I-4 XIN, XOUT Pin fIN1 f = 10 to 50 MHz f = 50 to 130 MHz f = 130 to 160 MHz fIN3 fIN4 f = 0.4 to 25 MHz *3 f = 8 to 12 MHz *4 f = 10 to 400 kHz *3 f = 400 to 500 kHz *3 f = 400 to 500 kHz *4 *5 Conditions Ratings min 200 40 20 40 40 40 40 70 40 20 70 10.25 typ max 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 10.35 MHz mVrms Unit
Notes: 1. Sine wave with capacitor coupled. 2. Pulse wave with DC coupled. 3. Serial data: CTC = 0 4. Serial data: CTC = 1 5. Recomended CI value for the crystal oscillator: CI 70 The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and other items. Therefore we recommend consulting with the manufacturer of the crystal for evaluation and reliability.
Electrical Characteristics in the Allowable Operating Ranges
Parameter Symbol Rf1 Rf2 Internal feedback resistance Rf3 Rf4 Rf5 Internal pull-down resistance Hysteresis Rpd1 Rpd2 VHIS VOH1 High-level output voltage VOH2 VOH3 VOL1 VOL2 VOL3 Low-level output voltage VOL4 XIN FMIN AMIN HCTR/I-3 LCTR/I-4 FMIN AMIN CE, CL, DI, LCTR/I-4 PDM1, PDM2, PDS, PDF AOUT1 XBUF PDM1, PDM2, PDS, PDF AOUT1 XBUF IO = - 1 mA IO = - 2 mA IO = - 1 mA IO = - 0.5 mA IO = 1 mA IO = 2 mA IO = 1 mA IO = 0.5 mA IO = 1 mA I/O-1, I/O-2, O-3 IO = 5 mA IO = 8 mA VOL5 VOL6 IIH1 IIH2 IIH3 High-level input current IIH4 IIH5 IIH6 IIH7 DO AOUT2 CE, CL, DI I/O-1, I/O-2 HCTR/I-3, LCTR/I-4 XIN FMIN, AMIN, HCTR/I-3, LCTR/I-4 AIN1, AREF TGI1, TGI2, TGO IO =1 mA IO = 5 mA IO = 1 mA, AIN2 = 1.3 V VI = 6.5 V VI = 13 V VI = VDD VI = VDD VI = VDD VI = 5.5 V VI = VDD 0.11 1.8 0.01 VDD - 1.0 VDD - 2.0 AVDD - 1.0 VDD - 1.5 1.0 2.0 1.0 1.5 0.2 1.0 1.6 0.2 1.0 0.5 5.0 5.0 5.0 0.9 15 100 3.0 nA A A V V 50 50 Pin Conditions Ratings min typ 1 500 500 500 500 100 100 0.1 VDD 300 300 k V k max Unit M
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No. 6976-5/29
LC72151V
Continued from preceding page.
Parameter Symbol IIL1 IIL2 IIL3 Low-level input current IIL4 IIL5 IIL6 IIL7 CE, CL, DI I/O-1, I/O-2 HCTR/I-3, LCTR/I-4 XIN FMIN, AMIN, HCTR/I-3, LCTR/I-4 AIN1, AREF TGI1, TGI2, TGO Pin VI = 0 V VI = 0 V VI = 0 V VI = 0 V VI = 0 V VI = 0 V VI = 0 V VIN = 8.5 V, I = 3 mA, AVDD = 8.5 V Analog switch on resistance RON TGI1, TGI2, TGO VIN = 4.5 V, I = 3 mA, AVDD = 8.5 V VIN = 0.5 V, I = 3 mA, AVDD = 8.5 V IOFF1 Output off leakage current IOFF2 IOFF3 High-level 3-state off leakage current Low-level 3-state off leakage current Input capacitance IOFFH IOFFL CIN IDD1 AOUT1 I/O-1, I/O-2, O-3, AOUT2 DO VO = 6.5 V VO = 13 V VO = 6.5 V 0.01 0.01 6 X'tal = 10.35 MHz fIN2 = 160 MHz VIN2 = 40 mVrms PLL block stopped (PLL INHIBIT) X'tal OSC operating (X'tal = 10.35 MHz) PLL block stopped (PLL INHIBIT) X'tal OSC stopped On-chip op-amp stopped PLL block stopped (PLL INHIBIT) X'tal OSC stopped On-chip op-amp stopped 10 18 70 50 70 0.11 1.8 0.01 Conditions Ratings min typ max 5.0 5.0 5.0 0.9 15 100 3.0 140 100 140 5.0 5.0 5.0 200 200 nA nA pF A nA A A Unit
PDM1, PDM2, PDS, PDF VO = VDD PDM1, PDM2, PDS, PDF VO = 0 V FMIN VDD
IDD2 Supply current IDD3
VDD
0.5
1.5
mA
AVDD
1.5
IDD4
VDD
10
A
No. 6976-6/29
LC72151V Pin Functions
Pin No. 30 1 Symbol XIN XOUT Usage * Crystal oscillator connection. (10.25 or 10.35 MHz) Function Pin circuit
X'tal OSC
* FMIN is selected by setting DVS in the control data to 1. * Enters high-speed locking mode by setting SNS in the control data to 1. 8 FMIN Local oscillator signal input * Enters normal mode by setting SNS in the control data to 0. * Input frequency: 10 to 160 MHz * The signal is transmitted to the swallow counter. * The divisor can be set to a value in the range 272 to 65,535. * AMIN is selected by setting DVS in the control data to 0. * When SNS in the control data is set to 1: Input frequency: 2 to 40 MHz 9 AMIN Local oscillator signal input The signal is directly transmitted to the swallow counter. * When SNS in the control data is set to 0: Input frequency: 0.5 to 10 MHz The signal is directly transmitted to the 12-bit programmable divider. The divisor can be set to a value in the range 5 to 4,095. 29 CE Chip enable * This pin must be set to the high level when inputting serial data to the LC72151V DI pin and when outputting serial data from the DO pin. * Serial data input for transferring data from the controller to the LC72151V. * Data synchronization clock signal used when inputting serial data to the LC72151V DI pin and when outputting serial data from the DO pin.
S
28
DI
Input data
S
27
CL
Clock
S
26
DO
Output data
* Serial data output for transferring data from the LC72151V to the controller.
* LC72151V power supply. A voltage in the range 4.5 to 5.5 V must be provided when the PLL circuit is operating. 6 VDD Power * The power-on reset circuit operates when power is first applied. Note: Power must be applied to AVDD before applied to VDD and AVDD must be higher than or equal to VDD. ------
7
VSS
Ground
* LC72151V ground. * Input/output dual function pins * The function will be selected according to IOC1 and IOC2 in the control data. Data = 0: Input port 1: Output port * When specified as an input port:
------
2 3
I/O-1 I/O-2
The input pin state is transmitted to the system microcontroller from DO pin. I/O ports Input state = Low: data is 0 = High: data is 1. * When specified as an output port: The output state will be determined according to I/O-1 and I/O-2 in the control data. Data = 0: Low = 1: Open * These pin function as an input port at a power-on reset.
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LC72151V
Continued from preceding page.
Pin No. Symbol Usage * Dedicated output pin 5 O-3 Output port * Latches OUT3 in the control data and outputs data from O-3 pin. * This pin goes open state at a power-on reset. Function Pin circuit
19 12 13 14 15
AIN1 AREF AVDD AVSS AOUT1 Op-amp for low-pass filter amp
* Op-amp for PLL active low-pass filter * AVSS is the analog system ground pin shared with low-pass filter Nch MOS transistor. * Voltage applied to AREF pin must be 1/2 that to VDD pin. Note: Power must be applied to AVDD before applied to VDD, and AVDD must be higher than or equal to VDD.
AVDD AIN1 - + AREF AVSS AOUT1
* PLL active low-pass filter Nch MOS transistor 24 25 AIN2 AOUT2 Transistor for low-pass filter amp * Source of the transistor is connected to AVSS pin. Note: Connect AVSS pin to ground in use.
AVSS
* PLL charge pump output 21 23 20 PDM1 PDM2 PDS Charge pump output When the frequency created by dividing the local oscillator signal frequency by N is higher than the reference frequency, a high level is output from the PD pin. When lower, a low level is output. The PD pin goes to the high-impedance state when the frequencies match. * PLL high-speed locking charge pump output 22 PDF PLL high-speed locking charge pump output When the high-speed locking mode is selected, signal pulses is output according to the frequency variation. This pin enters highimpedance state when the local oscillation frequency enters the set frequency range.
TGI1
18 17 16 TGI1 TGI2 TGO PLL high-speed locking TG * PLL high-speed locking active low-pass filter transmission gate input/output dual function pins Note: Connect AVSS pin to ground in use.
TGO TGI2
* HCTR is selected by setting CTS1 in the control data to 1. Input frequency: 0.4 to 25 MHz The signal is input to a divide-by-2 circuit and the result is input to a general-purpose counter. This counter can also be used as an integrating counter. The counter value is output as the result of the count, MSB first, from the DO pin. There are four measurement periods: 4, 8, 32, and 64 ms. * When H/I-3 in the control data is set, this pin functions as an input port, and the value is output from the output pin DO. * LCTR is selected by setting CTS1 in the control data to 1. * When the LCTR is selected as described above and CTS0 is set to 1: This pin enters the frequency measurement mode. Input frequency: 10 to 500 kHz The signal is directly transmitted to the general-purpose counter. * When CTS0 is set to 0 This pin enters period measurement mode. 11 LCTR/I-4 General-purpose counter Input frequency: 1 Hz to 20 kHz Period can be measured either in single period or in double period. If double period measurement is selected, the frequency is 2 Hz to 40 kHz. The counter value is output as the result of the count, MSB first, from the DO pin. * When L/I-4 in the control data is set: This pin functions as an input port, the value is output from the output pin DO.
10
HCTR/I-3
General-purpose counter
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LC72151V
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Pin No. Symbol Usage Function * Output buffer for the crystal oscillator circuit 4 XBUF Crystal oscillator buffer * When XB in the serial data is set to 1, the output buffer operates and the crystal oscillator signal (a pulse signal) is output. When XB is 0, XBUF outputs a low level. After the power-on reset, the output buffer is fixed at the low level. XOUT Pin circuit
Serial Data I/O Methods Data is input to and output from the LC72151V using the Sanyo CCB (Computer Control Bus) format, which is the serial bus format used by SANYO audio ICs. This IC adopts a CCB format with an 8-bit address.
I/O mode Address B0 B1 B2 B3 A0 A1 A2 A3 * Control data input (serial input) mode. [1] IN1 (82) 0 0 0 1 0 1 0 0 * 32 bits of data are input. * See the "DI Control Data (Serial Data Input) Structure" item for details on the content of the input data. * Control data input (serial input) mode. [2] IN2 (92) 1 0 0 1 0 1 0 0 * 32 bits of data are input. * See the "DI Control Data (Serial Data Input) Structure" item for details on the content of the input data. * Data output (serial data output) mode. [3] OUT (A2) 0 1 0 1 0 1 0 0 * The number of bits output is equal to the number of clock cycles. * See the "DO Output Data (Serial Data Output) Structure" item for details on the content of the output data. Content
I/O mode determined
CE
1 CL 2
DI
B0
B1
B2
B3
A0
A1
A2
A3
First Data IN1/2
1 DO 2
First Data OUT First Data OUT
1 CL: Normally Hi 2 CL: Normally Low
No. 6976-9/29
(2) IN2 mode
(1) IN1 mode
DI
DI
(6) I/O-C
I/O-1 I/O-2
P0 P1 P2 P3 P4 P5 Address Address
(17) Don't Care
* *
10010100
00010100
(7) O-PORT
(18) XTAL
OUT1 OUT2 OUT3 XB XS
DI control data (serial data input) structure
(17) Don't Care
*
(1) P-CTR
(12) TLR-D
(13) CWS-D
LC72151V
(14) HSTMR
TLR0 TLR1 CWS0 CWS1 HSE0 HSE1 H/I-3
(8) U/I-C L/I-4 CTP CTC IL0
(5) U-CTR
(2) PD-C
(4) DO-C
(3) R-CTR
(9) Unlock
(10) PD-L
(4) DO-C (16) Reset
(11) DZ-C
IL1 ULD UL0 UL1 DLC DZ0 DZ1 TEST0 TEST1 TEST2 TEST3
* : Don't care
(15) TEST
(5) U-CTR
P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 SNS DVS PDC0 PDC1 R0 R1 R2 R3 DT0 DT1 RST CTE CTS0 CTS1 GT0 GT1
No. 6976-10/29
LC72151V DI control data description
No. Control block/data Content * This data sets the divisor for the programmable divider and P15 is the MSB of this binary value. LSB will change according to the DVS and SNS. Related data
DVS 1 1 0 0 Programmable divider data (1) P0 to P15 DVS, SNS
SNS 1 0 1 0
LSB P0 P0 P0 P4
Set divisor (N) 272 to 65535 272 to 65535 272 to 65535 4 to 4095
*: When the LSB is P4, P0 to P3 are invalid. * Used to select programmable divider signal input pins (FMIN, AMIN) and to switch the input frequency range. DVS 1 1 0 0 SNS 1 0 1 0 Input pin FMIN FMIN AMIN AMIN Input pin frequency range 10 to 160 MHz (High-speed mode) 10 to 160 MHz (Normal mode) 2 to 40 MHz 0.5 to 10 MHz
*: When the DVS and SNS are set to 1, the high-speed locking mode is selected, the highspeed control data becomes valid. By setting DVS to 1 and SNS to 0 this pin enters FMIN mode, the sub-charge pump control data is valid, the high-speed locking control data becomes invalid. * This data controls the sub-charge pump. PDC1 0 1 Sub-charge pump control data PDC0, PDC1 1 PDC0 * 1 0 Sub-charge pump state High impedance Charge pump operating (at all times) Charge pump operating (when PLL unlocked) HSE0 HSE1 (* : don't care)
(2)
* The sub-charge pump can be used in conjunction with the PDM1 or the PDM2 pin (main charge pump pin) to form a high-speed locking circuit. *: FMIN(High-speed mode): Setting DVS and SNS to 1 forces the sub-charge pump to operate for the time set due to the high-speed locking end flag output wait time, and allows the locking time to be reduced after switching to the normal PLL mode. See the "Charge Pump Structure" item for details. * Reference frequency selection data R3 0 0 0 0 0 0 0 0 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency (kHz) 50 50 25 25 12.5 6.25 3.125 3.125 10 9 5 1 3 30 PLL inhibit + X'tal OSC stop PLL inhibit
(3)
Reference divider data R0 to R3
1 1 1 1 1 1 1 1
Note: PLL inhibit (backup mode) The programmable divider block is stopped, the FMIN and AMIN pins are pulled down to ground, and the charge pump output is set to the floating state.
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LC72151V
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No. Control block/data Content * Data that determines the output of the DO pin ULD 0 0 0 0 1 1 1 1 DT1 0 0 1 1 0 0 1 1 DT0 0 1 0 1 0 1 0 1 DO pin Low when unlocked Open end-UC *1 IN *2 Open Open end-UC *1 IN *2 Related data
*Note: Open state will be selected at the power-on reset. Note: *1. end-UC: General-purpose counter operation completion check
DO (1) Start (2) Completion (3) CE: HI
CTE (1) When the count operation starts by setting end-UC with CTE set to 1 from 0, DO pin automatically goes to open state. (2) When the general-purpose counter operation ends, the DO pin goes low, it is allowed to check the count end. (3) DO pin goes to open state according to the serial data input/output state: CE pin = high. Note: *2. IL1 0 0 1 1 IL0 0 1 0 1 Open I-1 (pin state) I-2 (pin state) DO goes low when I-1 changes. IN I/O-1 I/O-2
DO pin control data (4) ULD DT0, DT1 IL0, IL1
However, if I/O-1 and I/O-2 are set to output mode, they change from IN to the open state. *: DO pin state during data input (IN1, IN2 modes, CE = high) keeps open regardless of the DO pin control data. In addition, Do pin during data input (OUT mode, CE = high) outputs the value for the internal DO serial data synchronized with the CL regardless of the DO pin control data. Caution: Cannot be used in crystal oscillator stop mode: R0 = 0, R1 = R2 = R3 = 1 (The DO pin will not change state.)
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LC72151V
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No. Control block/data Content * Selects the general-purpose counter input pins (HCTR, LCTR). CTS1 1 0 0 CTS0 * 1 0 Input pin HCTR LCTR LCTR Measurement mode Frequency Frequency Period Related data
* General-purpose counter measurement start data CTE = 1: Starts the counter. CTE = 0: Resets the counter. General-purpose counter control data CTS0, CTS1 (5) CTE GT0, GT1 CTP CTC 0 0 1 1 0 1 0 1 4 ms 8 32 64 GT1 GT0 Frequency measurement Measurement time Wait time CTP = 0 CTP = 1 Period measurement mode One period One period Two periods Two periods * Determines the measurement time (frequency mode) and number of periods (period mode).
3 to 4 ms 1 to 2 ms 3 to 4 ms 1 to 2 ms 7 to 8 ms 1 to 2 ms 7 to 8 ms 1 to 2 ms
* When CTE = 0, input pull-down is disabied by setting CTP to 1 Note: Wait time: 1 to 2ms. However, CTP must be set to 1 4ms before CTE is set to 1. * The input sensitivity is reduced when CTC is set to 1. (Sensitivity: 10 to 30 mV rms) *: Refer to the General-purpose counter stracture on page 22 for details.
* Data that specifies the I/O direction of the I/O ports (I/O-1, I/O-2). (6) I/O port control data IO-1, I/O-2 [Data] = 0: Input port 1: Output port *: After the power-on reset, the I/O-1 and I/O-2 are set up as input ports. * Data that determines the output from output ports O-1 to O-3. Output port data OUT1 to OUT3 [Data] = 0: Open 1: Low *: Invalid when the corresponding port is set up as an input port. *: At a power-on reset, open state is selected by selling the data to 0 * Data that switch the function between general-purpose counter and input port. General-purpose counter (8) control data H/I-3, L/I-4 L/I-4 = H/I-3 = 0: I-3 (input port) 1: HCTR (gereal-purpose counter) 0: I-4 (input port) 1: LCTR (gereal-purpose counter) CTS0, CTS1 I/O-1, I/O-2 OUT1, OUT2
(7)
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LC72151V
Continued from preceding page.
No. Control block/data Content * Width selection for the phase error (oE) detection function used to determine the PLL locked/unlocked state. When a phase error greater than the oE detection width from the table occurs, the PLL circuit is seen as in the unlocked state. UL1 0 0 UL0 0 1 oE detection width Stopped 0 0.49 s 1 0 0.49 s 0.43 s (9) Unlock state detection data UL0, UL1 1 1 0.97 s 0.87 s 0.98 s Detection output Open Directly outputs oE oE is extended by 0.1 to 0.2 ms. oE is extended by 0.11 to 0.22 ms. oE is extended by 0.1 to 0.2 ms. oE is extended by 0.1 to 0.2 ms. oE is extended by 0.11 to 0.22 ms. oE is extended by 0.1 to 0.2 ms. X'tal 10.25 M/10.35 MHz 10.25 M/10.35 MHz 10.25 MHz 10.35 MHz (fr = 30/9/3 k) 10.35 MHz (Other than fr = 30/9/3 k) 10.25 MHz 10.35 MHz (fr = 30/9/3 k) 10.35 MHz (Other than fr = 30/9/3 k) ULD DT0, DT1 Related data
oE DO 0.1 to 0.22ms Extended
Unlock state output
*: When unlocked, the DO pin goes low and the serial data output is UL = 0. * Bit that forcible sets the charge pump output to the low level. DLC = 1: Low level (10) Charge pump control data DLC DLC = 0: Normal operation *: If a deadlock occurs due to the VCO control voltage (Vtune) going to zero and stopping the VCO oscillator, set the charge pump output to the low level and set Vtune to VCC to escape from the deadlocked state (deadlock clearing circuit). Normal operation is selected after the power-on reset. * Controls the phase comparator dead band. DZ1 0 (11) Phase comparator control data DZ0, DZ1 0 1 1 DZ0 0 1 0 1 Dead band mode DZA DZB DZC DZD
*: The phase comparator operates in DZA mode after the power-on reset. (Recomended modes: DZD, DZC) * Data to control the frequency in the convergence range to judge the high-speed locking control completion. This data is valid when FMIN (high-speed mode) is selected by setting DVS and SNS to 1. TLR1 TLR0 (12) High-speed locking convergence range control data TLR0, TLR1 0 0 1 1 0 1 0 1 Convergence range [kHz] 50 100 150 200 DVS SNS
*:The convergence range is 200 kHz at a power-on reset. Refer to Description of the High-Speed Locking Control System (P.19) for details.
Continued on next page.
No. 6976-14/29
LC72151V
Continued from preceding page.
No. Control block/data Content * Data to control the wait time in the high-speed locking. This data is valid when the FMIN (high-speed mode) is selected by setting DVS and SNS to 1. CWS1 CWS0 (13) High-speed locking charge wait time control data CWS0, CWS1 0 0 1 1 0 1 0 1 Wait time [s] 2.5 5 10 20 DVS SNS Related data
*:The wait time is 20 s at a power on reset. Refer to Description of the High-Speed Locking Control System (P.19) for details. * Data to control the wait time after the high-speed locking control completes till the operation is switched to the normal PLL operation. This data is valid when the FMIN (high-speed mode) is selected by setting DVS and SNS to 1. During the wait time, the unlock signal is forcibly output, the sub-charge pump allows to be operated. Thereby, reduces the locking time after switching to the normal PLL operation. (14) High-speed locking completion flag output wait time control data HSE0, HSE1 HSE1 HSE0 0 0 1 1 0 1 0 1 Wait time [s] 0 200 400 800
DVS SNS PDC0 PDC1
*:The wait time is 400 s at a power on reset. Refer to Description of the High-Speed Locking Control System (P.19) for details. * IC test control data IC test data TEST0 (15) TEST1 TEST2 TEST3 These bits must be set as follows during normal operation. TEST0 = 0 TEST1 = 0 TEST2 = 0 TEST3 = 0 *: After the power-on reset, the test data is all set to zero. * This data resets the LC72151V. *: After the power is first applied, the power-on reset circuit initializes the IC. However, the data must be set to 1 to ensure the initialization. * Set data to 0 * Crystal oscillator selection data XS = 0: 10.25 MHz Crystal oscillator circuit (18) XS XB = 1: 10.35 MHz * Crystal oscillator buffer (XBUF) XB = 0: Buffer output is turned off. XB = 1: Buffer output is turned on. *: XB = 0: Buffer output is turned off at a power-on reset. Note: After power is first applied, the power-on reset circuit initializes the IC. However, the CCB data (RST) must be input to the IC to ensure the initialization. R0 to R3
(16)
Reset RST
(17)
DNC
No. 6976-15/29
LC72151V Structure of the DO Output Data (serial output data) (3) OUT mode
Address DI 0 1 0 1 0 1 0 0
C19
C18
C17
C16
C15
C14
C13
C12
C11
UL
C9
C8
C7
C6
C5
C4
C3
C2
C1
(1) IN-PORT
(2) UNLOCK
(3) IF-CTR
*: Bits that are set to 0.
No.
Control block/data
Content * The bits I1 to I4 are set to the latched states of the I/O pins I/O-1 and I/O-2 and the input pins HCTR/I-3 and LCTR/I-4. These states are latched at the point the IC enters data output mode. The pin states are latched regardless of the pin mode (input or output). I1, I2 I/O-1 and I/O-2 pin states I3, I4 HCTR/I-3 and LCTR/I-4 pin states Pin state = high: 1 low: 0
C0
I4
I3
I2
I1
DO
C10
* * *
****
Related data
I/O-1 I/O-2 H/I-3 L/I-4
(1)
I/O port data I4 to I1
(2)
PLL unlock data UL
* Data created by latching the value for the unlock detection circuit UL 0: Unlocked 1: Locked or in detection halt mode
UL0 UL1
(3)
IF counter binary counter C19 to C0
* Data created by latching the value for the IF counter (20-bit binary counter) C19 MSB of the binary counter C0 LSB of the binary counter
CTE GT0 GT1
No. 6976-16/29
LC72151V Serial data input (IN1/IN2) (1) CL: Normally high
tEL CE tES tEH
tSU, tHD, tEL, tES, tEH, > 0.45 s
tLC < 0.45 s
CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data
(2) CL: Normally low
tEL CE tES tEH
CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data
Serial data output (OUT) (1) CL: Normally high
tSU, tHD, tEL, tES, tEH > 0.45 s
tDC, tDH < 0.2 s
tEL CE
tES
tEH
CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I4 tDC I3 I2 I1 C3 C2 C1 tDH C0
(2) CL: Normally low
tEL CE tES tEH
CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I4 tDC I3 I2 I1 C3 C2 C1 tDH C0
Note: The DO pin is an n-channel open drain output, and thus the data switching time will differ depending on the value of the pull-up resistor used and the printed circuit board capacitance.
No. 6976-17/29
LC72151V Serial data timing
CE tCH CL VIH DI VIL DO tSU tHD VIL VIH VIL VIH tCL VIL
VIH
VIL VIH tEH
VIH tEL tES
VIL
tDC
tDC
tDH
tLC Internal data latch operation Old New

CE tCL CL VIH VIL VIH DI VIL DO tSU tHD VIL VIH tCH VIH
VIH
VIL
VIL tEL tES
VIH tEH
tDC
tDH
Internal data latch operation
tLC Old New

Allowable Operating Ranges at Ta = -40 to 85C, VSS = 0 V
Parameter Data setup time Data hold time Clock low-level period Clock high-level period CE wait time CE setup time CE hold time Data latch change time Data output time Symbol tSU tHD tCL tCH tEL tES tEH tLC tDC tDH DO, CL DO, CE Depends on the value of the pull-up resistor used. DI, CL DI, CL CL CL CE, CL CE, CL CE, CL Pin Conditions Ratings min 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.2 typ max Unit s s s s s s s s s
Note: See the timing chart for serial data transfers.
No. 6976-18/29
LC72151V Description of the High-Speed Locking Control System The LC72151V realizes the maximum inter-band edge high-speed locking time 500 s by optimizing the filter constants and internal status setting when the FMIN (high-speed mode) by setting DVS and SNS to 1. The following describes the high-speed locking control system. Procedure The LC72151V operates as shown below when selecting FMIN (high-speed mode) and setting sub-charge pump operation during unlocked.
PDF/PDM1/PDM2/PDS/TGI1/TGI2 pin states PDF Change value N New high-speed locking control (When the value N variation is under 16, only operates the normal PLL.) Operates normal PLL when the local oscillation frequency enters the high-speed locking frequency range. (The sub-charge pump operates for the time set by the high-speed locking completion flag output wait time.) Stops the sub-charge pump and only the main-charge pump operates. (Normal locking state) *: : operating; : stopped (high-impedance) PDM1 PDM2 PDS TGI1 TGI2
Control Data Setting data (CCB) necessary for the new high-speed locking control is described below. This data is valid when the FMIN (high-speed mode) is selected by setting DVS and SNS to 1.
CCB data Name (Selectable set value) Description The new high-speed locking control controls the convergence of the target frequency into the set frequency range. TLR0/TLR1 High-speed locking convergence range (50/100/150/200 kHz) This data can be used to set the frequency range for convergence judgement. *: As the convergence range narrower, the locking time tends to be shorter. During the new high-speed locking control, charge application from the PDF pin and local oscillation frequency measurement for the FMIN pin are repeatedly implemented. CWS0/CWS1 High-speed locking charge wait time (0/2.5/5/10 s) This data can be used to set the Vt voltage stable time after the charge is applied until the local oscillator frequency is measured. *: Voltage stable time Vt changes according to the peripheral circuit. After the new high-speed locking control ends, since the phase remains in convergence state in the internal unlock detection circuit until the locking judgement is implemented, the sub-charge pump will not operate by the sub-charge pump operation setting during unlocked. This data can be used to set the time to force the sub-charge pump to operate for after the new high-speed locking control completes. *: After the new high-speed locking control completes, the locking time tends to be shortened by operating the sub-charge pump for an adequate time. *: The recommended values are for reference purpose only, not the guarantee values for the fastest locking time. Recommended value
TLR0 = 0 TLR1 = 0 (50 kHz)
CWS0 = 1 CWS1 = 0 (5 s)
HSE0/HSE1
High-speed locking completion flag output wait time (0/100/200/400 s)
HSE0 = 0 HSE1 = 1 (400 s)
No. 6976-19/29
LC72151V Block Diagram
XIN
Reference Divider
Phase Detector
PDM2 PDM1
FMIN
Programmable Divider
CCB (CE,DI,CL)
Register
Unlock
Register
Unlock Detector and Subcharge Pump Cont
PDS
Fast Lock Up Register Control
PDF
Frequency Counter Gate Time System Clock for Fast Lock Up Control TGI1
TGI2
- +
TGO
AOUT
AVSS
AREF
AIN1
AVDD
VCO
No. 6976-20/29
LC72151V Charge Pump Structure
TLR0,TLR1 Fast Lock Up CWS0,CWS1 Control HSE0,HSE1 (High Speed) PDF New high-speed locking charge pump
DLC (MAIN) fvco/N Phase Detector fref (MAIN) DZ0 DZ1
PDM1
Main-charge pump
PDM2
Main-charge pump
Clock UL0 UL1
Unlock Detector and Subcharge Pump Cont
PDS Unlock (SUB)
Conventional high-speed locking sub-charge pump
PDC0
PDC1
DO
PDC1 0 1 1
PDC0 * 1 0
PDS(Sub-charge pump state) High impedance Charge pump operating (at all times) Charge pump operating (when PLL unlocked)
DLC 0 1
PDM1, PDM2, PDS Normal operation Forced low
Note: If the unlock state is detected when the channel changes, the sub-charge pump (PDS) operates. Since the subcharge pump operates concurrently with the main-charge pump, decrease the time constants for the low-pass filter to accelerate the locking. However, note that when the FMIN (high-speed mode) is selected and when the channel changes (during highspeed locking control), both the main- and the sub-charge pumps do not operate and enter the high impedance state, and forcibly implement an unlock judgement. When locked at a high-speed locking control completion, the output is not extended but locking is instantaneously judged. By selecting sub-charge operation (during unlocked) with FMIN (high-speed mode) selected, the sub-charge pump is forcibly operated to shorten the locking time for the time set by the high-speed locking completion flag output wait time control data (HSE0, HSE1) after switching from high-speed locking control to normal PLL operation.
No. 6976-21/29
LC72151V General-purpose counter structure
1 2 (FIF) LCTR Single period/ double period extraction circuit Check signal 4/8/32/64 ms GT1,GT0 GT (T) I/O signal switching gate S1 S2 S3 L S B 0-3 4-7 8-11 CTE CTS1 CTS0 C = FIF x GT C = (1/T) / 900kHz General-purpose counter (20-bit binary counter) M S B 12-15 16-19
HCTR
DO pin
Parameter X'tal OSC Check signal
LCTR period measurement mode check signal frequency 10.25 MHz 1025 kHz 10.35 MHz fref = 30, 9, 3 kHz 1030 kHz fref = other than 30, 9, 3 kHz 1150 kHz
CTS1 S1 S2 S3 1 0 0
CTS0 * 1 0
Input pin HCTR LCTR LCTR
Measurement mode Frequency Frequency Period
Frequency range 0.4 to 25.0 MHz 10 to 500 kHz 1.0 to 20 x 103 Hz
Input sensitivity 40 mVrms *1 40 mVrms *1 (Pulse)
*1: CTC = 0: 40 mVrms CTC = 1: 70 mVrms HCTR: Minimum input sensitivity regulation CTC 0 (Normal mode) 1 (Degrade mode) 0.4 f < 8 40 mVrms -- 8 f < 12 40 mVrms (5 to 15 mVrms) 70 mVrms (40 to 60 mVrms) f [MHz] 12 f 25 40 mVrms --
LCTR: Minimum input sensitivity regulation CTC 0 (Normal mode) 1 (Degrade mode) 10 f< 400 40 mVrms --
f [MHz]
400 f 500 20 mVrms (1 to 10 mVrms) 70 mVrms (15 to 30 mVrms)
--: No stipulation ( Not guaranteed) ( ): Actual value (Reference value)
GT1 0 0 1 1
GT0 0 1 0 1
Frequency measurement mode Measurement time 4 ms 8 32 64 7 to 8 ms Wait time 3 to 4 ms
Period measurement mode 1 period
2 periods
CTC: Input sensitivity select data. Input sensitivity is degraded by setting CTC to 1. However, the actual value for HCTR is in the range 40 to 60 mVrms at 10.7 MHz, for LCTR is in the range 15 to 30 mVrms at 450 kHz. CTP: Input pull-down can be inhibited by setting CTP to 1. Set CTP to 1 4 ms before setting CTE to 1. Set CTP to 0 when the counter is not used. Wait time will be reduced to 1 to 2 ms by setting CTP to 1.
No. 6976-22/29
LC72151V The LC72151V's general-purpose counter is a 20-bit binary counter. The result of the count operation can be read out MSB first from the DO pin. The measurement time when the general-purpose counter is used for frequency measurement is set to either 4, 8, 32, or 64 ms by the GT0 and GT1 bits. The frequency of the input to the HCTR pin can be measured by determining how many pulses were input to the general-purpose counter during this measurement time. When the general-purpose counter is used to measure the frequency, the period of the signal input to LCTR pin can be measured by counting the number of check signals input to the general-purpose counter for the one or two periods of the signal input to the LCTR pin. Reset the general-purpose counter in advance by setting CTE to 0 before starting the counter. A general-purpose counter count operation is started by setting the CTE bit in the serial data to 1. The serial data takes effect internally to the LC72151V when the CE pin input level is changed from high to low. The input to the HCTR pin must be provided before the wait time has elapsed after CE was set low. Next, the result of the general-purpose counter count after the measurement completes must be read out while CTE is still set to 1. This is because the general-purpose counter is reset when CTE is set to 1. Never fail to reset the general-purpose counter before starting the count operation of the general-purpose counter. In addition, the signal input to LCTR pin is directly transmitted to the general-purpose counter. Note that the signal input to the HCTR pin is first divided by 2 internally to the IC and then input to the general-purpose counter. Therefore, the result of the general-purpose counter count is a value that corresponds to 1/2 of the frequency actually input to the HCTR pin.
CE
CTE=1 Measurement time
GT tWU Start Completion end-UC TWU : Wait time
When used as an integrating counter
CTE=1 CE Internal data latch (CTE) GT Generalpurpose counter end-UC (DO) Start Restart End of the count operation
*CTE: 0 1 * Resets the general-purpose counter * Starts the general-purpose counter * Restarts the counter if set to 1 again.
CTE=1
CTE=0
Integrates Reset
End of the count operation
In integrating count mode, the count value of the general-purpose counter is accumulated. Care must be taken to handle counter overflow correctly. The count value will be in the range 0H to FFFFFH.
No. 6976-23/29
LC72151V Other items (1) Notes on the phase detector dead band
DZ1 0 0 1 1 DZ0 0 1 0 1 Dead band mode DZA DZB DZC DZD Charge pump ON/ON ON/ON OFF/OFF OFF/OFF Dead band - -0 s -0 s +0 s ++0 s
When the charge pump operates in ON/ON mode, the charge pump generates correction pulses even when the PLL is locked. Here, it is easy for the loop to become unstable, and special care is required in designs that use this mode. The following problems may occur in ON/ON mode. * Side bands may be generated due to reference frequency leakage. * Side bands may be generated due low-frequency leakage due to the envelope of the correction pulses. When a dead band is present (OFF/OFF mode), the loop will be stable, but it will be harder to acquire a good C/N ratio. On the other hand, with the mode that does not have a dead band (ON/ON mode), it will be easier to acquire a high C/N ratio, but harder to acquire loop stability. Therefore, the DZA and DZB modes, in which there is no dead band, can be effective if either a high signal-to-noise ratio of 90 to 100 dB in FM reception or an increased pilot margin in AM stereo reception is required. Inversely, if such a high FM signal-to-noise ratio is not required for FM reception, or an adequate pilot margin can be acquired for AM stereo reception, then the DZC and DZD modes, in which a dead band is present, may be more effective. Dead zone (dead band) definition The phase comparator compares fp with the reference frequency (fr) as shown in figure 1. This circuit outputs a voltage V (A) that is proportional to the phase difference o as shown in figure 2. However, due to internal delays and other factors, the actual IC is unable to compare small phase differences, and thus a dead zone (B) appears in the output. To achieve a high signal-to-noise ratio in the end product, the dead zone should be as small as possible. However, in popularly-priced models, there are cases where a somewhat wider dead zone may be easier to work with. This is because in some situations, such as when a powerful signal is applied to the RF input, in popularly-priced models there may be RF leakage from the mixer to the VCC. When the dead zone is narrow, outputs to correct this leakage are output, that output in turn modulates the VCO, and generates a beat signal with the RF.
V RF Leakage MIX (B) fp Programmable divider Dead zone Phase detector LPF VCO o (nsec) (A)
fr Reference divider
Figure 1
Figure 2
(2) Notes on the FMIN, AMIN, HCTR/I-3, and LCTR/I-4 pins The coupling capacitor must be located as close as possible to these pins. A capacitance of approximately 100 pF is desirable. In particular, if the HCTR/I-3 and LCTR/I-4 pin capacitor is over about 1000 pF, the time required to reach the bias level may become excessive, and incorrect counting may occur due to the relationship with the wait time.
No. 6976-24/29
LC72151V (3) Notes on the IF counting using HCTR/I-3 and LCTR/I-4 pins When counting the IF frequency, the application microcontroller must test the state of the IF IC SD (station detect) signal, and only if the SD signal is present, turn on the IF counter buffer output and perform an IF count operation. Methods in which auto-search operations are implemented only using the IF count may incorrectly stop at frequencies where no station is present due to leakage from the IF counter buffer. (4) Using the DO pin At times other than data output mode, the DO pin can also be used to check for general-purpose counter count operation completion, to output the unlock state detection signal, and to check for changes in the input pins. Note that the states of the input pins (I/O-1 and I/O-2) can be directly input to the system microcontroller through the DO pin. (5) Power supply pins Capacitors of at least 0.1 F must be inserted between the VDD and VSS power supply pins and between AVDD and AVSS to reduce noise. These capacitors must be located as close to the VDD and VSS, AVDD and AVSS pins as possible. Additionally, power must be applied to AVDD before applying to VDD, and AVDD must be higher than or equal to VDD. (6) Note on power application After power is first applied, the power-on reset circuit initializes the IC. However, the CCB data RST must be set to 1 to ensure the initialization. (7) Notes on VCO design The VCO must be designed so that the VCO oscillation does not stop if the control voltage (Vtune) becomes 0 V. If it is possible for this oscillator to stop, use the charge pump control data (DLC) to forcible set Vtune to VCC temporarily to prevent the PLL circuit from deadlocking. (This function is called a deadlock clear circuit.) Pin states during a power-on reset
State Power-on state XOUT F F I-1 I-2 I/O-1 I/O-2 XBUF O O-3 VDD VSS FMIN AMIN HCTR/I-3 LCTR/I-4 AREF AVDD AVSS AOUT1 XIN CE DI CL DO AOUT2 Power-on state State
LC72151V
AIN2 PDM2 PDF PDM1 PDS AIN1 TGI1 TGI2 TGO
O: Open
L: Low
F: Floating
No. 6976-25/29
LC72151V Sample Application Circuit
10.25M/10.35MHz
XOUT
1
30 XIN 29 CE -COM CE
I/O-1
2
S
I/O-2 2nd Mixer 330 XBUF 33pF O-3
3
S
28 DI 27 CL
DI
4
S
CL
5
26 DO VCC=8V 3.9k 25 AOUT2
DO
Unlock SD end-UC U-Count ST-Indic
VDD
6
AVSS
Tuner-System
0.068F 24 AIN2 4.3k 5.6k
3.3k AMVCO 0.01F
VSS 100pF FMIN 100pF AMIN 100pF
7
8
23 PDM2 200
9
22 PDF 8.2k 21 PDM1
HCTR/I-3 10
22k VCC =8V
LCTR/I-4 11 VCC=8V AREF 12 10k AVDD 13
20 PDS 19 AIN1 100 18 TGI1 4700pF
AVSS 14
17 TGI2 2k 100 FMVCO 1000pF 16 TGO 0.033F
AOUT1 15
ST-Indicate FM/AM-IF
FM/AM IF-Request SD
*: The constants shown are for reference purpose only, but do not guarantee the operation. Notes: 1. Power must be applied to AVDD before applying to VDD, and AVDD must be higher than or equal to VDD. 2. AREF is an op-amp reference input voltage pin and must be applied a voltage 1/2 VDD. The applied voltage requires to be applied from another power supply from VDD to prevent affections due to logic system noise or other factors.
No. 6976-26/29
LC72151V LC72151V State Setting Examples 1. In the case of FMRF 87.5 MHz reception (X'tal = 10.35 MHz/IF = +10.8 MHz) FM VCO = 98.3 MHz X'tal = 10.35 MHz, fref = 50 kHz : XS = 1, R0 = R1 = R2 = R3 = 0 FMIN (high-speed mode) selected : DVS = 1, SNS = 1 Dead-zone mode = DZD : DZ0 = DZ1 = 1 Programmable divider divisor 98.3 MHz / 50 kHz = 1966 07AE (Hex) High-speed locking control conditions High-speed locking convergence range = 50 kHz : TLR0 = TLR1 = 0 High-speed locking charge wait time = 5 s : CWS0 = 1, CWS1 = 0 High-speed locking completion flag output wait time = 400 s : HSE0 = 0, HSE1 = 1 Unlock detection width = 0.43 s : UL0 = 0, UL1 = 1
[IN1]
Address 8 DI 2
00010100
First Data IN1 LSB MS B E A 7 0 B 0 0 0 01110101111000001101000000000000 SNS DVS PDC0 PDC1 CTS0 CTS1 DT1 RST CTE GT0 GT1 TEST2 TEST3 R1 R2 R3 DT0 P8 P9 P10 P11 P12 P13 P14 P15 R0 P0 P1 P2 P3 P4 P5 P6 P7 Transmitted data
[IN2]
Address 9 DI 2
10010100
First Data IN2 LSB MS B 0 * *00*** 1 9 0 0 D 0 0100010010000000010110000 TEST0 TEST1 TLR0 TLR1 CWS0 CWS1 HSE0 HSE1 H/I-3 L/I-4 CTP CTC IL1 ULD UL0 UL1 DLC DZ0 DZ1 IL0 XS Transmitted data
*
OUT1 OUT2 OUT3 XB
I/O-1 I/O-2
* *
*
No. 6976-27/29
LC72151V 2. In the case of AMRF 530 kHz reception (X'tal = 10.35 MHz/IF = 10.8 MHz) AM VCO = 11.330 MHz X'tal = 10.35 MHz, fref = 10 kHz : XS = 1, R0 = R1 = R2 = 0, R3 = 1 X'tal Buffer ON : XB = 1 AMIN selected : DVS = 0, SNS = 1 Dead-zone mode = DZD : DZ0 = DZ1 = 1 Programmable divider divisor 11.330 MHz / 10 kHz = 1133 046D (Hex) [IN1]
Address 8 DI 2
00010100
First Data IN1 LSB MSB D 6 4 0 1 8 0 0 10110110001000001000000100000000 DVS PDC0 PDC1 CTS0 CTS1 SNS DT1 RST CTE GT0 GT1 TEST2 TEST3 R1 R2 R3 DT0 P10 P11 P12 P13 P14 P15 R0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 Transmitted data
[IN2]
Address 9 DI 2
10010100
First Data IN2 LSB MSB * *00* 8 ** 1 0 0 0 D 0 1100000000000000010110000 TEST0 TEST1 TLR0 TLR1 CWS0 CWS1 HSE0 HSE1 H/I-3 L/I-4 CTP CTC IL1 ULD UL0 UL1 DLC DZ0 DZ1 IL0 Transmitted data
*
OUT1 OUT2 OUT3 XB XS
I/O-1 I/O-2
* *
*
No. 6976-28/29
LC72151V Locking time (Reference data)
98.2MHz 118.7MHz 118.7MHz 98.2MHz
ZOOM ZOOM
0.41ms
0.39ms
10kHz
10kHz
*: Data here are measured using a SANYO evaluation board with the peripheral circuits and state setting shown in the Sample Application Circuit and the LC72151V State Setting Examples.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 2002. Specifications and information herein are subject to change without notice. PS No. 6976-29/29

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